ARM Cortex-A75

ARM Cortex-A75
General information
Launched	2017
Designed by	ARM Holdings
Max. CPU clock rate	to 3.0 GHz
Cache
L1 cache	128 KB (64 KB I-cache with parity, 64 KB D-cache) per core
L2 cache	256–512 KB
L3 cache	1–4 MB
Architecture and classification
Application	Mobile; Network Infrastructure; Automotive designs; Servers
Instruction set	ARMv8.2-A
Physical specifications
Cores	1–8 per cluster, multiple clusters;
Products, models, variants
Product code name	Prometheus;
History
Predecessors	ARM Cortex-A73; ARM Cortex-A72; ARM Cortex-A17
Successor	ARM Cortex-A76

The ARM Cortex-A75 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings's Sophia design centre. The Cortex-A75 is a 3-wide decode out-of-order superscalar pipeline.^[1] The Cortex-A75 serves as the successor of the Cortex-A73, designed to improve performance by 20% over the A73 in mobile applications while maintaining the same efficiency.^[2]

Design

According to ARM, the A75 is expected to offer 16–48% better performance than an A73 and is targeted beyond mobile workloads. The A75 also features an increased TDP envelope of 2 W, enabling increased performance.^[3]

The Cortex-A75 and Cortex-A55 cores are the first products to support ARM's DynamIQ technology.^[2]^[3] The successor to big.LITTLE, this technology is designed to be more flexible and scalable when designing multi-core products.

Licensing

The Cortex-A75 is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).

ARM has also collaborated with Qualcomm for a semi-custom version of the Cortex-A75, used within the Kryo 385 CPU.^[4] This semi-custom core is also used in some Qualcomm's mid-range SoCs as Kryo 360 Gold.