Capability Hardware Enhanced RISC Instructions

Capability Hardware Enhanced RISC Instructions (CHERI) is a computer processor technology designed to improve security. CHERI aims to address the root cause of the problems that are caused by a lack of memory safety in common implementations of languages such as C/C++, which are responsible for around 70% of security vulnerabilities in modern systems.[1][2]

The hardware works by giving each reference to any piece of data or system resource its own access rules. This prevents programs from accessing or changing things they should not. It also makes it hard to trick a part of a program into accessing or changing something that it should be able to access, but at a different time. The same mechanism is used to implement privilege separation, dividing processes into compartments that limit the damage that a bug (security or otherwise) can do.

CHERI can be added to many different instruction set architecture s including MIPS, AArch64, and RISC-V, making it usable across a wide range of platforms.

Software must be recompiled to gain fine-grained memory-safety benefits from CHERI, but most software requires few (if any) changes to the source code.[3] CHERI's importance has been recognised by governments as a way to improve cybersecurity and protect critical systems.[4] It is under active development by various business and academic organizations.[5]

Background

CHERI is a capability architecture.[6] Early capability architectures, such as the CAP computer and Intel iAPX 432, demonstrated secure memory management but were hindered by performance overheads and complexity.[7] As systems became faster and more complex, vulnerabilities like buffer overflows and use-after-free errors became widespread. CHERI addresses these challenges with a design intended for modern computing environments. It enforces memory safety and provides secure sharing and isolation to handle increasing software complexity and combat cyberattacks.

Mechanism

Memory access with and without CHERI.

A CHERI system operates at a hardware level by providing a hardware-enforced type (a CHERI capability) that authorises access to memory. This type includes an address and other metadata, such as bounds and permissions. Instructions such as loads, stores, and jumps, that access memory use one of these types to authorise access, whereas on traditional architectures they would simply use an address.

This metadata is stored inline, alongside the address, in the computer's memory is protected by a tagged bit, which is cleared if the capability is tampered with. This informs the computer of which areas of memory can be accessed through a specific operation and how a program can modify or read memory through that operation. This allows CHERI systems to catch cases where memory that was outside the bounds of where the program was supposed to read or write to was operated on. Associating the metadata with the value used to access memory, rather than with the memory being accessed (in contrast to a memory management unit) means that the hardware can catch cases where a program attempts to access a part of memory that it should have access to while intending to access a different piece of memory.

Implementations of CHERI systems also include modifications to the default memory allocator. A memory allocator is a component that defines that a range of addresses should be treated by the programmer as an object. On a CHERI system, it must also communicate this information to the hardware, by setting the bounds on the pointer (represented by a CHERI capability) that is returned.[8] It may also communicate the lifetime, to prevent use-after-free or use-after-reuse bugs.[9][10][11]

Depending on the context, CHERI systems can be used to enhance compiler-level checks, build secure enclaves,[12] or even be used to augment existing instruction architectures. A report by Microsoft in 2019 found that CHERI's protections could be used to mitigate over 70% of memory safety issues found in 2019 at the company.[13] CHERI architectures are also designed to be backward compatible with existing programming languages such as C and C++. A study performed by University of Cambridge researchers found that porting six million lines of C and C++ code to CHERI required changes to 0.026% of the Lines-of-Code (LoC).[3]

Limitations

The architecture introduces hardware complexity due to the tag-bit mechanisms and capability checks required for enforcing memory safety. Although optimisations have been implemented to minimise these impacts[14], the performance trade-offs can vary depending on specific workloads and specific implementations. Additionally, CHERI requires modifications to both software and hardware ecosystems. Implementations such as Morello allow unmodified binaries to run but these do not get any additional security benefits. Software must be recompiled or adapted to utilise CHERI's capability-based model, and hardware manufacturers must incorporate CHERI extensions into their designs.

Standardisation remains an ongoing effort. While initiatives such as the CHERI Alliance and RISC-V standardisation[15] aim to establish broader support, the lack of widely accepted industry standards for CHERI features have delayed adoption. Adapting legacy software or retrofitting existing systems to work with CHERI can be challenging, particularly for large and heterogeneous codebases. The difficulty often stems from programming practices used during the software's original development, such as implementing custom memory management, where identifying pointers from integers can be particularly problematic.[16]

CHERI implementations

The CHERI architecture has been implemented across multiple platforms and projects:

• Morello: Developed by Arm as part of the UKRI-funded Digital Security by Design (DSbD) programme,[17][18] the Morello chip is a superset architecture designed to evaluate experimental CHERI features for potential production use on the AArch64 architecture. The Morello board supports CheriBSD, custom versions of Android, and Linux. It remains a research prototype.
• CHERIoT:[10] Introduced by Microsoft in 2023[19] and now developed by multiple vendors,[20] CHERIoT is a RISC-V CHERI adaptation optimised for small embedded devices. CHERIoT is a hardware-software co-designed project and builds a custom RTOS and compartment model along with specialised hardware to provide string security guarantees. It incorporates advanced memory safety features inspired by the CHERI temporal safety projects performed on Morello.
• Sonata:[21] Developed by lowRISC and manufactured by NewAE as part of the UKRI-funded Sunburst project, the Sonata platform is an FPGA-based system designed to run RISC-V architectures. The board has an open-source design, allowing researchers and developers to modify and adapt its hardware and software. Sonata is primarily designed as a prototyping system for CHERIoT.
• ICENI: Announced by SCI Semiconductors in 2024,[22] ICENI is a CHERIoT-compatible microcontroller designed for secure embedded systems.

CHERI implementations that target mainstream operating systems, are designed to accommodate both legacy and pure capability software, to allow for gradual adaptation for existing applications. CHERI has also been implemented across various hardware architectures in a research setting, including MIPS,[6] AArch64 (via the Morello platform), and RISC-V.[23]

History

In the 1970s and 1980s early capability architectures such as the CAP computer (developed at the University of Cambridge) and the Intel iAPX 432 demonstrated strong security properties. These systems relied on indirection tables to manage capabilities, introducing performance bottlenecks as memory access required multiple lookups. While this approach worked when processors were slow and memory was fast, it became impractical by the mid-1980s as processors became faster and memory access times lagged behind.[7]

In 2010 DARPA launched the Clean-slate design of Resilient, Adaptive, Secure Hosts (CRASH) programme,[24][25] which tasked participants with redesigning computer systems to improve security. SRI International and University of Cambridge team revisited capability architectures, seeking to address memory safety challenges inherent in conventional designs.

By 2012 early CHERI prototypes were presented,[26] These prototypes ran a microkernel with hand-written assembly for manipulating capabilities. CHERI was designed to be easy to implement on modern superscalar pipelined architectures. Unlike earlier capability systems, CHERI eliminated the need for indirection tables,[6] avoiding the associated performance issues and proving that modern capability architectures could be efficiently implemented.

In 2014 CHERI hardware demonstrated its ability to run a full UNIX-like operating system, FreeBSD. This demonstration showed that CHERI's capability model can integrate with existing software ecosystems. CHERI was originally prototyped as an extension to MIPS-64.[6] The implementation used 256-bit capabilities, containing fields for a 64-bit base, length, object type, and permissions, with some bits reserved for experimental purposes.

In 2015 CHERI introduced a new capability encoding model that separated the address (referred to as a cursor) from the bounds and permissions. This refinement allowed capabilities to function as pointers in compiled C code,[11] improving usability. That same year, Arm joined the project and provided critical feedback, highlighting that while doubling pointer sizes might be acceptable, quadrupling them would not. This feedback led to the development of CHERI Concentrate,[14] a compressed encoding model that reduced capability size to 128 bits by eliminating redundancy between the base, address, and top.

In 2019 CheriABI[27] demonstrated a fully memory-safe implementation of POSIX, allowing existing desktop software to become memory safe with a single recompile.

By 2020 it became evident that software vendors were reluctant to port their software without hardware vendor support, while hardware vendors were unwilling to produce chips without sufficient customer demand. UK Research and Innovation (UKRI) launched the Digital Security by Design (DSbD) programme[28] to address adoption barriers for CHERI. The programme allocated £70M, matched by £100M of industrial investment, to build the CHERI software ecosystem.[28]

This initiative funded Arm's Morello chip, a superset architecture designed to evaluate experimental CHERI features for potential production use based on AArch64. The Morello board was designed to run CheriBSD, as well as custom versions of Android and Linux. At the same time, the Cornucopia[29] project demonstrated that CHERI could enforce both spatial and temporal memory safety, offering deterministic protection against heap object temporal aliasing (roughly, "use-after-free"). The follow-up project, Cornucopia Reloaded,[9] showcased efficient temporal safety using page-table features in Morello, in particular, near-negligible pause times for the application making use of revocation.

In 2023 Microsoft introduced CHERIoT[10], a RISC-V CHERI adaptation optimised for small embedded devices. CHERIoT incorporated ideas from Cornucopia and memory colouring techniques such as SPARC ADI and Arm MTE to enhance security. As part of the UKRI-funded Sunburst project, lowRISC launched the Sonata platform to advance RISC-V-based CHERI development and support standardisation efforts. Both the CHERI RISC-V research work and CHERIoT fed into the standardisation process for an official CHERI family of RISC-V extensions.[15] Codasip announced that they had RISC-V IP cores with CHERI extensions available to license.[30]

By 2024 SCI Semiconductors announced ICENI,[22] a CHERIoT-compatible chip designed specifically for secure embedded systems. Codasip is actively developing a Linux kernel implementation for the RISC-V architecture.[31] The CHERI Alliance, a non-profit organisation based in Cambridge, UK, was established to promote the adoption of CHERI technology and its integration into secure digital products and systems, including Google as a founding member.[5]

References

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