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Forte Design Systems
Forte Design Systems, Inc. was a San Jose, CA, based provider of high-level synthesis (HLS) software products, also known as electronic system-level (ESL) synthesis. Forte's main product was Cynthesizer. On February 14, 2014, Forte was acquired by Cadence Design Systems.[1] HistoryThe company was founded in 1998 as C2 Design Automation by John Sanguinetti, Andy Goodrich and Randy Allen. A year later the company changed its name to CynApps and began selling C-based synthesis and RTL translation tools. It also distributed an open-source C++ class library called Cynlib, which competed with SystemC. In 2000, CynApps acquired Dasys, a Pittsburgh-based maker of behavioral synthesis tools. In 2001, CynApps merged with Chronology (founded in Redmond, WA, in 1990) to become Forte Design Systems. Forte began selling Cynthesizer, a SystemC-based HLS tool, which had its first successful tapeout in Japan in 2001. In 2009, Forte acquired Arithmatica, whose CellMath Designer tool was integrated into Cynthesizer. In 2012 and 2013, industry analysts found that Cynthesizer was used by 31% of high-level designers, the most of any ESL tool. On February 14, 2014, Cadence Design Systems acquired Forte. In 2015, Cadence released Stratus HLS, which combines the automation and synthesis engine of Cynthesizer with the graphical features of Cadence's previous HLS tool, C-to-Silicon. Management team
ProductCynthesizer is a high-level synthesis tool. "High level" in this context means designers can describe the functionality of a complex electronic system as a pure algorithm in SystemC. The designer can then direct Cynthesizer to produce a unique hardware architecture that implements the system in a specific number of clock cycles. This replaces the traditional method of using a hardware description language like Verilog or VHDL, where the designer must manually write out the usage of hardware components in a fixed schedule of clock cycles. If designers want hardware with different performance, they can redirect Cynthesizer to produce a new architecture that is faster or smaller, whereas with the traditional method a completely new design must be written. The output of Cynthesizer is Verilog, which is then run automatically through a logic synthesis tool. References
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